1. Technical Field
A semiconductor device fabricating technique is disclosed. More Specifically, a semiconductor device with a capacitor, and a fabricating method for the same is disclosed.
2. Description of the Related Art
In a semiconductor device, the capacitance of a capacitor C is expressed by εA/d (where ε is the dielectric constant, A is the surface area, and d is the thickness of the dielectric medium). That is, the capacitance is proportional to the surface area of the storage electrode and to the dielectric constant of the dielectric medium.
Accordingly, in semiconductor fabricating processes in which the semiconductor device is becoming smaller, in order to secure the required level of capacitance, the structure of the storage electrode is three-dimensional, thereby increasing the surface area of the storage electrode. In the alternative, a high dielectric constant material such as BST[(Ba,Sr)TiO3] is used to secure the required capacitance. The three-dimensional structures require a complicated fabricating process, and therefore, this method brings a rise in manufacturing costs and a reduction in yield. Meanwhile, the use of the high dielectric constant material such as BST causes degradation of the current leakage characteristics, because it is difficult to maintain the oxygen stoichiometry.
In the capacitor using BST, highly oxidation-resistant noble metals such as Pt, Ru and the like have to be used, but these metals are too stable. Accordingly, not only is etching difficult, but also a dry etching such as sputtering has to be used, with the result that a vertical profile cannot be easily obtained.
In order to solve these problems, the following method has been studied. Specifically, a sacrificial film such as an oxide film is utilized to form a capacitor pattern. Then one of the noble metals is deposited by applying the electrochemical deposition method (hereinafter, referred to as ‘ECD’), and an etch-back is carried out.
FIGS. 1A to 1C are sectional views of the conventional fabricating method for the semiconductor device. First, as shown in FIG. 1A, a transistor is formed on a substrate 11. That is, a word line (not illustrated) and a source/drain 12 are formed on the substrate 11, and then, an interlayer insulating film 13 is deposited on the substrate 11.
Then the interlayer insulating film 13 is selectively etched to form a contact hole so as to expose relevant parts of the source/drain 12. Then polysilicon is deposited on the entire surface including the contact hole, and then, an etch-back or a chemical mechanical polishing (to be called CMP below) is carried out to form a polysilicon plug 14 within the contact hole.
Then a platinum seed layer 15 is formed on the polysilicon plug 14, and then, a capacitor sacrificial film 16 is deposited on the platinum seed layer 15. Here, the platinum seed layer 15 is for forming a lower electrode by carrying out the electrochemical deposition method (ECD). A Physical Vapor Deposition method (to be called PVD below) is carried out to form the platinum seed layer 15.
Then a photoresist film is spread on the capacitor sacrificial film 16, and then the photoresist film is patterned by an exposure and a development to form a storage node mask 17. Then by using the mask 17, the capacitor sacrificial film 16 is dry-etched by using CF4, CHF3 or C2F6 to open a concave part 18 by which the platinum seed layer 15 is exposed.
Then as shown in FIG. 1B, a bias is supplied to the platinum seed layer 15, and a platinum lower electrode 19 is deposited on the exposed platinum seed layer 15 by applying the electrochemical deposition method. Then the capacitor oxide film 16 is etched to expose the portion of the platinum seed layer 15, on which the platinum lower electrode 19 has not been formed. Then the exposed platinum seed layer 15 is removed by an etch-back. Under this condition, the platinum seed layer 15 is divided, and therefore, the platinum lower electrode 19 is divided between the adjacent cells.
Then as shown in FIG. 1C, a BST film 20 is deposited on the entire surface including the platinum lower electrode 19 by applying the chemical vapor deposition (to be called CVD below) method. Then an upper electrode 21 is deposited on the BST film 20 by applying the CVD method. However, in the conventional technique as described above, when forming the open part by etching the capacitor sacrificial film, the mask pattern upon the sacrificial film may cause a misalignment. In this case, the upper face of the plug is exposed when carrying out an etching to remove the seed layer.
In FIG. 2, the elements same as those of FIGS. 1A to 1C are assigned with the same reference codes. As shown in the portion A of FIG. 2, the BST film and a barrier layer (for forming the plug 14) are directly contacted to each other, and therefore, the dielectric property of the BST film is degraded.